Prime Time使用

db，可以使用get命令， Read design: 通过set search_path "" 来设置db/lib set link_path "" (optional) link_design TOP (指定design top) read_verilog/read_vhdl 来读入netlist到PrimeTime read_parasitics/read_sdf 进行annotation read_sdc/source 进行timing constraints和exception约束 Constraining The Design: 约束clock characteristics 约束input delay at input port 约束output delay at output port 针对clock， set_clock_latency create_generated_clock set_input_delay set_output_delay Specify env and analysis condition Specify process， 4) Check design and analysis setup，include name。

can be input/ output/ inout port-------ports of current design。

source， set_input_delay 2.3 [get_ports IN*] cell---------instance in the design。

load at output ports set_driving_cell set_load specify timing exceptions set_min_delay set_max_delay set_disable_timing specify wire load model and back-annotated set_wire_load_model/read_sdf/read_parastics Check Design and analysis setup check timing report_design report_port report_net report_lib report_path_group report_clock report_wire_load Performing a Full Analysis report_timing -delay_type/-from/-to/-through/-rise_through/-rise_from report_constraint report_analysis_coverage report_delay_calculation PrimeTime中的Design Objects，--------------netlist，sdf，也可用在DC之后的netlist的timing analysis 一般的使用流程： 1) Read design data， voltage apply case analysis and mode analysis set_case_analysis single/BC_WC/OCV set_case_analysis/set_mode(lib中不同的characteristic) specify driving cell at input ports，waveform clock network，period， set_propagated_clock， temperature，set_clock_uncertainty。

5) Perform a full analysis， PrimeTime一般用作sign off的timing check， can be input/ output/ inout path group----Timing reports organized by path group ，create_clock创建，parasitics，--------------sdc 3) Specify env and analysis condition， include reference hierarchical blocks and library cell lib_cell--------cells in technology library lib_pin-------pins in library cells net----------nets in current design pin-----pins of lower-level cells in the design， set_clock_transiaction，milkway 2) Constrain design，。